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M28W800T M28W800B
8 Mbit (512Kb x16, Boot Block) Low Voltage Flash Memory
PRELIMINARY DATA
s
s
s s
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s s
s s
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s s
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SUPPLY VOLTAGE - VDD = 2.7V to 3.6V: for Program, Erase and Read - VDDQ = 1.65V or 2.7V: Input/Output option - VPP = 12V: optional Supply Voltage for fast Program and Erase ACCESS TIME - 3.0V to 3.6V: 100ns - 2.7V to 3.6V: 120ns PROGRAMMING TIME: 10s typical PROGRAM/ERASE CONTROLLER (P/E.C.) - Program Word-by-Word - Status Register bits COMMON FLASH INTERFACE - 64 bit Security Code OTP MEMORY AREA MEMORY BLOCKS - Parameter Blocks (Top or Bottom location) - Main Blocks BLOCK ERASE BLOCK PROTECTION on TWO PARAMETER BLOCKS (selected without 12V supply) PROGRAM/ERASE SUSPEND - Read or Program another Block during Program/Erase Suspend PROGRAM/ERASE LATENCY TIME: <1s - Data update on a Word-by-Word basis - Efficient data Read/Write during Program/Erase suspend FAST RECOVERY from POWER DOWN LOW POWER CONSUMPTION - Automatic Stand-by: 10A max - Stand-by: 10A max - 100,000 Program/Erase cycles per block 20 YEARS OF DATA RETENTION - Defectivity below 1ppm/year ELECTRONIC SIGNATURE - Manufacturer Code: 0020h - Device Code, M28W800T: 8892h - Device Code, M28W800B: 8893h
BGA
TSOP48 (N) 12 x 20 mm
BGA48 (GB) 8 x 6 solder balls
Figure 1. Logic Diagram
VDD VPP VDDQ 19 A0-A18 W E G RP WP M28W800T M28W800B 16 DQ0-DQ15
VSS
AI02607
May 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M28W800T, M28W800B
Figure 2A. BGA Connections (Top View)
1 2 3 4 5 6 7 8
A
A13
A11
A8
VPP
WP
A7
A4
B
A14
A10
W
RP
A18
A17
A5
A2
C
A15
A12
A9
A6
A3
A1
D
A16
DQ14
DQ5
DQ11
DQ2
DQ8
E
A0
E
VDDQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
F
VSS
DQ7
DQ13
DQ4
VDD
DQ10
DQ1
G
AI02608
Note: Although no Solder Ball is present where the unnamed dotted connections are placed (A6, C4 and C5 locations), these are reserved for future use. Routing should be avoided in this area.
Figure 2B. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP VPP WP NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 VDDQ VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
Table 1. Signal Names
A0-A18 DQ0-DQ7 DQ8-DQ15 E G W RP WP VDD VDDQ VPP VSS NC Address Inputs Data Input/Output, Command Inputs Data Input/Output Chip Enable Output Enable Write Enable Reset / Deep Power-Down Write Protect Supply Voltage Optional Power Supply for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Not Connected Internally
12 13
M28W800T M28W800B
37 36
24
25
AI02609
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M28W800T, M28W800B
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO VDD, VDDQ VPP Parameter Ambient Operating Temperature (2) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage Value -40 to 85 -40 to 125 -55 to 155 -0.6 to VDDQ+0.6 -0.6 to 4.2 -0.6 to 13.5 Unit C C C V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range.
DESCRIPTION The M28W800 is a 8 Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. The device is offered in the TSOP48 (12 x 20 mm) and the BGA48 0.75mm ball pitch packages. When shipped, all bits of the M28W800 are in the '1' state. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Each block can be programmed and erased over 100,000 cycles. V DDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up the program phase at customer production line environment. An internal Command Interface (C.I.) decodes the instructions to access/modify the memory content. The Program/Erase Controller (P/E.C.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. Verification is performed too, unburdening the microcontroller, while the Status Register tracks the status of the operation. The following instructions are executed by the M28W800: Read Array, Read Electronic Signature, Read Status Register, Clear Status Register, Program, Block Erase, Program/Erase Suspend, Program/Erase Resume, CFI Query.
Organisation The M28W800 is organised as 512 Kbits by 16 bits. A0-A18 are the address lines; DQ0-DQ15 are the Data Input/Output. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. A Reset/Power-Down controls the hardware reset and the power-down. The upper two (or lower two) parameter blocks can be protected to secure the code content of the memory. WP controls protection and unprotection operations. Memory Blocks The device features an asymmetrical blocked architecture. The M28W800 has an array of 23 blocks: 8 Parameter Blocks of 4 KWord and 15 Main Blocks of 32 KWord. M28W800T has the Parameter Blocks at the top of the memory address space while the M28W800B locates the Parameter Blocks starting from the bottom. The memory maps are shown in Tables 3 and 4. The two upper parameter blocks can be protected from accidental programming or erasure, using WP. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed.
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M28W800T, M28W800B
Table 3. Top Boot Block Address
Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 7F000-7FFFF 7E000-7EFFF 7D000-7DFFF 7C000-7CFFF 7B000-7BFFF 7A000-7AFFF 79000-79FFF 78000-78FFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF
Table 4. Bottom Boot Block Address
Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address Range 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
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M28W800T, M28W800B
SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A18). The address signals are inputs driven with CMOS voltage levels. They are latched during a write operation. Data Input/Output (DQ0-DQ15). The data inputs, a word to be programmed or a command to the C.I., are latched on the Chip Enable E or Write Enable W rising edge, whichever occurs first. The data output from the memory Array, the Electronic Signature or Status Register is valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected, the outputs are disabled or RP is tied to VIL. Commands are issued on DQ0-DQ7. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at V IL. Output Enable (G). The Output Enable controls the data Input/Output buffers. Write Enable (W). This input controls writing to the Command Register, Input Address and Data latches. Write Protect (WP). Write Protect is an input to protect or unprotect the two lockable parameter blocks. When WP is at VIL, the lockable blocks are protected. Program or erase operations are not achievable. When WP is at V IH, the lockable blocks are unprotected and they can be programmed or erased (refer to Table 9). Reset/Power Down Input (RP). The RP input provides hardware reset of the memory and power down functions. When RP is at VIL, the memory is in reset/deep power down mode. The outputs are put to High-Z and the current consumption is minimised. When RP is at VIH, the device is in normal operation. Exiting reset/deep power down mode the device enters read array mode. proVDD Supply Voltage (2.7V to 3.6V). VDD vides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). It ranges from 2.7V to 3.6V. VDDQ Supply Voltage (1.65V to VDD+0.3V). VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or it can use a separate supply. It can be powered either from 1.65V to 2.2V or from 2.7V to 3.6V. VPP Program Supply Voltage (12V). VPP is the power supply for program and erase operations. The M28W800 is intended to execute program and erase operations at VDD voltage ranges. Nevertheless, customers wishing to speed up programming at their manufacturing environment can also apply 12V to VPP. This is not intended for extended use. VPP can be connected to 12V for a total of 80 hours maximum. 12V may be applied to VPP during program and erase for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. Stressing the device beyond these limits could damage the device. VPP may be tied to 5V during read or idle phases. 5V supply is forbidden for program or erase operations. The V PP must be supplied with either 2.7V to 3.6V or 11.4V to 12.6V during programming or erase operations. VPP can be tied to VSS to achieve a complete block protection. VSS Ground. VSS is the reference for all the voltage measurements.
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M28W800T, M28W800B
DEVICE OPERATIONS Four control pins rule the hardware access to the Flash memory: E, G, W, RP. The following operations can be performed using the appropriate bus cycles: Read, Write the Command of an Instruction, Output Disable, Standby, Power Down (see Table 5). Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the CFI. Both Chip Enable (E) and Output Enable (G) must be at VIL in order to perform the read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output independently of the device selection. The data read depend on the previous command written to the memory (see instructions RD, RSIG, RSR, RCFI and RDO). Read Array is the default state of the device when exiting power down or after power-up. Write. Write operations are used to give Commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable E and Write Enable W are at V IL with Output Enable G at VIH. Commands, Input Data and Addresses are latched on the rising edge of W or E, whichever occur first. Output Disable. The data outputs are high impedance when the Output Enable G is at V IH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable E is at VIH and the device is in read mode. The power consumption is reduced to the standby level and the outputs are set to high impedance, independently from the Output Enable G or Write Enable W inputs. If E switches to VIH during program or erase operation, the device enters in standby when finished. Power Down. During power down all internal circuits are switched off, the memory is deselected and the outputs are put in high impedance. The memory is in Power Down when RP is at V IL. The power consumption is reduced to the Power Down level, independently from the Chip Enable E, Output Enable G or Write Enable W inputs. If RP is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid as it has been compromised by the aborted operation.
Table 5. User Bus Operations (1)
Operation Read Write Output Disable Standby Power Down E VIL VIL VIL VIH X G VIL VIH VIH X X W VIH VIL VIH X X RP VIH VIH VIH VIH VIL WP X X X X X VPP Don't Care VDD or VPPH Don't Care Don't Care Don't Care DQ15-DQ0 Data Output Data Input Hi-Z Hi-Z Hi-Z
Note: 1. X = VIL or VIH, VPPH = 12V 5% .
Table 6. Read Electronic Signature (RSIG Instruction)
Code Manufact. Code M28W800T Device Code M28W800B
Note: 1. RP = VIH.
Device
E VIL VIL VIL
G VIL VIL VIL
W VIH VIH VIH
A0 VIL VIH VIH
A18-A1 Don't Care Don't Care Don't Care
DQ15-DQ8 00h 88h 88h
DQ7-DQ0 20h 92h 93h
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INSTRUCTIONS AND COMMANDS Twelve instructions are available (see Tables 7 and 8) to perform Read Memory Array, Read Status Register, Read Electronic Signature, CFI Query, Erase, Program, Clear Status Register, Program/Erase Suspend, Program/Erase Resume, Read OTP, Program OTP. Status Register output may be read at any time, during programming or erase, to monitor the progress of the operation. An internal Command Interface (C.I.) decodes the instructions while an internal Program/Erase Controller (P/E.C.) handles all timing and verifies the correct execution of the Program and Erase instructions. P/E.C. provides a Status Register whose bits indicate operation and exit status of the internal algorithms. The Command Interface is reset to Read Array when power is first applied, when exiting from power down or whenever V DD is lower than VLKO. Command sequence must be followed exactly. Any invalid combination of commands will reset the device to Read Array. Read (RD) The Read instruction consists of one write cycle (refer to Device Operations section) giving the command FFh. Next read operations will read the addressed location and output the data. When a device reset occurs, the memory is in Read Array as default. Read Status Register (RSR) The Status Register indicates when a program or erase operation is complete and the success or failure of operation itself. Issue a Read Status Register Instruction (70h) to read the Status Register content. The Read Status Register instruction may be issued at any time, also when a Program/Erase operation is ongoing. The following Read operations output the content of the Status Register. It is latched on the falling edge of E or G signals, and can be read until E or G returns to VIH. Either E or G must be toggled to update the latched data. Additionally, any read attempt during program or erase operation will automatically output the content of the Status Register. Read Electronic Signature (RSIG) Two codes identifying the manufacturer and the device can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the M28W800. Manufacturer and Device Code (Electronic Signature) can be read by a Read Electronic Signature Instruction. It uses 3 operations: a write operation issues the command 90h; it is followed by two read operations to output the manufacturer and device codes. The Manufacturer Code, 20h, is output when the address line A0 is at V IL. The Device Code is 8892h (top version) or 8893h (bottom version) and is output when A0 is at VIH (refer to table 4). Other Address inputs are ignored. The codes are output on DQ0-DQ15. Return to Read Mode is achieved writing the Read Array command. CFI Query (RCFI) The Common Flash Interface Query mode is entered by writing 98h. Next read operations will read the CFI data. Write a read instruction to return to Read mode (refer to the Common Flash Interface section). Read OTP Area (RDO) The Read OTP Area (RDO) instruction is a single write cycle instruction: as the command 80h is written the device will be driven in Read OTP mode. Any successive read bus cycle will output the addressed OTP word. To return in the Read Memory Array mode write the Read command FFh. Table 7. Commands
Hex Code 00h, 01h, 60h, 2Fh, C0h 10h 20h 30h 40h 50h 70h 80h 90h 98h B0h D0h FFh Command Invalid/Reserved Alternative Program Set-up Erase Set-up OTP Program Set-up Program Set-up Clear Status Register Read Status Register OTP Read Read Electronic Signature CFI Query Program/Erase Suspend Program/Erase Resume, or Erase Confirm Read Array
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M28W800T, M28W800B
Table 8. Instructions
Mnemonic RD RSR 1st Cycle Instruction Read Memory Array Read Status Register Read Electronic Signature CFI Query Read OTP Area Erase Program Program OTP Area Clear Status Register Program/Erase Suspend Program/Erase Resume Cycles Operation 1+ 1+ Write Write Address (1) X X Data FFh 70h Operation Read (2) Read (2) Read (2) Read (2) Read (2) Write Write Write 2nd Cycle Address Read Address X Signature Address (3) CFI Address OTP Address Block Address Address OTP Address Data Data Status Register Signature Query OTP Data D0h Data Input OTP Data Input
RSIG RCFI RDO EE PG PDO CLRS PES PER
1++ 1+ 1+ 2 2 2 1 1 1
Write Write Write Write Write Write Write Write Write
X X X X X X X X X
90h 98h 80h 20h 40h or 10h 30h 50h B0h D0h
Note: 1. X = Don't Care. 2. The first cycle of the RD, RSR, RSIG or RCFI instruction is followed by read operations to read memory array, Status Register or Electronic Signature codes. Any number of Read cycle can occur after one command cycle. 3. Signature address bit A0=VIL will output Manufacturer code. Address bit A0=V IH will output Device code. Other address bits are ignored.
Erase (EE) Block erasure sets all the bits within the selected block to '1'. One block at a time can be erased. It is not necessary to program the block with 00h as the P/E.C. will do it automatically before erasing. This instruction uses two write cycles. The first command written is the Erase Set up command 20h. The second command is the Erase Confirm command D0h. An address within the block to be erased is given and latched into the memory during the input of the second command. If the second command given is not an erase confirm, the status register bits b4 and b5 are set and the instruction aborts. Read operations output the status register after erasure has started. Status Register bit b7 returns '0' while the erasure is in progress and '1' when it has completed. After completion the Status Register bit b5 returns '1' if there has been an Erase Failure.
Erasing should not be attempted when V PP is not within the allowed range of values (V DD or VPPH) as the results will be uncertain. Status Register bit b3 returns a '1' if VPP is not within the allowed range of values when erasing is attempted and/or during erasing execution. Refer to the signals description section for details of the allowable ranges. Erase aborts if VPP drops out of the allowed range or RP turns to VIL. As data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated. A Clear Status Register instruction must be issued to reset b3 of the Status Register. During the execution of the erase by the P/E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions.
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Table 9. Memory Blocks Protection Truth Table
VPP (1,3) X VIL VDD or VPPH (5) VDD or VPPH (5)
Note: 1. 2. 3. 4. 5.
RP (2,4) VIL VIH VIH VIH
WP (1,4) X X VIL VIH
Lockable Blocks Protected Protected Protected Unprotected
Other Blocks Protected Protected Unprotected Unprotected
Notes:1.X' = Don't Care RP is the Reset/Power Down. VPP is the program or erase supply voltage. VIH/VIL are logic high and low levels. VPP must be also greater than the Program Voltage Lock-Out VPPLK.
Table 10. Status Register Bits
Mnemonic Bit Name Logic Level '1' P/ECS 7 P/E.C. Status '0' Erase Suspend Status '1' '0' '1' ES 5 Erase Status '0' PS 4 Program Status '1' '0' '1' VPPS 3 VPP Status '0' Program Suspend Status '1' '0' Erase Success Program Error Program Success VPP Invalid, Abort VPP OK Suspended In Progress or Completed Program/Erase on protected Block, Abort No operation to protected blocks Busy Suspended In progress or Completed Erase Error Definition Ready Note Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits b4 or b5 for Program or Erase Success On an Erase Suspend instruction P/ECS and ESS bits are set to '1'. ESS bit remains '1' until an Erase Resume instruction is given. ES bit is set to '1' if P/E.C. has applied the maximum number of erase pulses to the block without achieving an erase verify. PS bit set to '1' if the P/E.C. has failed to program a word. VPPS bit is set if the VPP voltage is not VPPH nor VDD when a Program or Erase instruction is executed. On a Program Suspend instruction P/ECS and PSS bits are set to '1'. PSS remains '1' until a Program Resume Instruction is given
ESS
6
PSS
2
BPS
1
Block Protection Status
'1'
BPS bit is set to '1' if a Program or Erase operation has been attempted on a protected block
'0' 0 Reserved
Note: Logic level '1' is High, '0' is Low.
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M28W800T, M28W800B
Program (PG) The memory array can be programmed word-byword. This instruction uses two write cycles. The first command written is the Program Set-up command 40h (or 10h). A second write operation latches the Address and the Data to be written and starts the P/E.C. Read operations output the Status Register content after the programming has started. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure. Programming should not be attempted when V PP is not within the allowed range of values (VDD or V PPH) as the results will be uncertain. Status Register bit b3 returns a '1' if VPP is not within the allowed range of values when programming is attempted and/or during programming execution. Refer to the signals description section for details. Programming aborts if VPP drops out of the allowed range or RP goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and re-programmed. A Clear Status Register instruction must be issued to reset b3 of the Status Register. During the execution of the program by the P/E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. Program OTP Area (PDO) The Program OTP Area (PDO) instruction is a two write cycle instruction: the first code issues is the OTP Program Setup command 30h, while during the second write cycle the OTP selected Address and the OTP Data to be written are applied to the device. The conventional Read Status Register operation can be performed to monitor the end of the programming operation. To return in the Read Memory Array mode write the Read command FFh. Clear Status Register (CLRS) The Clear Status Register uses a single write operation which clears bits b3, b4 and b5 to '0'. Its use is necessary before any new operation when an error has been detected. Note, also, that the Read Array command must be issued before data can be read from the memory array. The Clear Status Register is executed writing the command 50h. Program/Erase Suspend (PES) As Erase takes in the order of seconds to complete, a Program/Erase Suspend instruction is provided. Program/Erase Suspend interrupts the Program/Erase routine allowing read from and program to data belonging to a different block. Program/Erase suspend is accepted only during the Program/Block Erase instruction execution. When a Program/Erase Suspend command is written to the C.I., the P/E.C. freezes the Program/ Erase operation. Program/Erase Resume (PER) continues the Program/Erase operation. Program/Erase Suspend consists of writing the command B0h without any specific address. The Status Register bit b2 is set to '1' when the program has been suspended. b2 is set to '0' in case the program is completed or in progress. The Status Register bit b6 is set to '1' when the erase has been suspended. b6 is set to '0' in case the erase is completed or in progress. The valid commands while erase is suspended are Program/Erase Resume, Program, Read Array, Read Status Register, Read Identifier, CFI Query. While program is suspended the same command set is valid except for program instruction. During program/erase suspend mode, the chip can be placed in a pseudo-standby mode by taking E to VIH. This reduces active current consumption. VPP must be maintained within the allowed range of values (V DD or VPPH) while program/erase is suspended. Program/Erase is aborted if VPP drops out of the allowed range or RP turns to VIL and Status Register b5 and b3 are set. Program/Erase Resume (PER) If a Program/Erase Suspend instruction was previously executed, the program/erase operation may be resumed by issuing the command D0h. The status register bit b2/b6 is cleared when program/erase resumes. Read operations output the status register after the program/erase is resumed. The suggested flow charts for programs that use the programming, erasure and program/erase suspend/resume features of the memories are shown from Figures 9, 10, 11 and 12.
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M28W800T, M28W800B
Table 11. Program, Erase Times and Program/Erase Endurance Cycles (TA = 0 to 70C or -40 to 85C; VDD = 2.7V to 3.6V)
M28W800 Parameter Test Conditions VPP = 12V 5% VPP = VDD VPP = 12V 5% VPP = VDD VPP = 12V 5% VPP = VDD VPP = 12V 5% VPP = VDD VPP = 12V 5% VPP = VDD 100,000 Min Typ (1) 10 20 0.24 0.8 0.03 0.1 0.6 1 0.4 0.5 1 2.4 0.12 0.3 5 5 4 4 Max Unit s s sec sec sec sec sec sec sec sec cycles
Word Program
Main Block Program
Parameter Block Program
Main Block Erase
Parameter Block Erase Program/Erase Cycles (per Block)
Note: TA = 25 C.
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M28W800T, M28W800B
BLOCK PROTECTION Two parameter blocks can be protected against Program or Erase to ensure extra data security. For M28W800T, the blocks from address 7E000h to 7FFFFh can be protected. For M28W800B, the blocks from address 00000h to 01FFFh can be protected. Unprotected blocks can be programmed or erased. WP tied to V IL protects the two lockable blocks. Any program or erase operation on protected blocks is aborted. The Status Register tracks when the event occurs. WP tied to VIH unprotects all the blocks that can be protect. Table 9 defines the protection methods. RP tied to VIL protects all blocks. POWER CONSUMPTION The M28W800 place itself in one of four different modes depending on the status of the control signals: Active Power, Automatic Power Savings, Standby and Power Down define decreasing levels of current consumption. These allow the memory power to be minimised, in turn decreasing the overall system power consumption. As different recovery time are linked to the different modes, please refer to the AC timing table to design your system. Active Power When E is at VIL and RP is at VIH, the device is in active mode. Refer to DC Characteristics to get the values of the current supply consumption. Automatic Stand-by Automatic Stand-by provides a low power consumption state during read mode. Following a read operation, after a delay close to the memory access time, the device enters Automatic Stand-by: the Supply Current is reduced to ICC1 values. The device keeps the last output data stable, till a new location is accessed. Stand-by Refer to the Device Operations section. Power Down Refer to the Device Operations section. Power Up The Supply voltage V DD and the Program Supply voltage VPP can be applied in any order. The memory Command Interface is reset on power up to Read Memory Array, but a negative transition of Chip Enable E or a change of the addresses is required to ensure valid data outputs. Care must be taken to avoid writes to the memory when VDD is above VLKO and VPP powers up first. Writes can be inhibited by driving either E or W to VIH. The memory is disabled until RP is up to V IH. Supply Rails Normal precautions must be taken for supply voltage decoupling, each device in a system should have the V DD and VPP rails decoupled with a 0.1F capacitor close to the V DD and VPP pins. The PCB trace widths should be sufficient to carry the required VPP program and erase currents. OTP MEMORY AREA M28W800 features an additional "One Time Programmable" Memory Area. This feature is obtained by means of an OTP Block of 256 word, which can be programmed once and cannot be erased, thus useful to store permanent data. This OTP memory area can be programmed and addressed in Read Mode by the customer through two dedicated commands. Refer to the Program OTP Area (PDO) and Read OTP Area (RDO) instructions to properly write and read the OTP memory block. The OTP Memory Area is organized as 256 x 16 bits as shown in the OTP Address Table, Figure 3.
Figure 3. OTP Memory Area Address Table
00000h OTP word # 0
000FFh
OTP word # 255
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COMMON FLASH INTERFACE (CFI) The Common Flash Interface (CFI) specification is a JEDEC approved, standardised data structure that can be read from the Flash memory device. CFI allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. CFI allows the system to easily interface to the Flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. Tables 12, 13, 14, 15, 16 and 17 show the address used to retrieve each data. Table 12. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional)
The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. Tables 12, 13, 14 and 15 show the addresses used to retrieve each data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 80h. This area can be accessed only in read mode by the final user and there are no ways of changing the code after it has been written by ST. Write a read instruction to return to Read mode. Refer to the CFI Query instruction to understand how the M28W800 enters the CFI Query mode.
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 13, 14, 15, 16 and 17. Query data are always presented on the lowest order data outputs.
Table 13. CFI Query Identification String
Offset 00h 01h 02h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0020h 0093h - bottom 0092h - top reserved 0051h 0052h 0059h 0003h 0000h offset = P = 0035h Address for Primary Algorithm extended Query table 0000h 0000h 0000h value = A = 0000h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) Address for Alternate Algorithm extended Query table note: 0000h means none exists Manufacturer Code Device Code Reserved Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Description
Note: Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
13/40
M28W800T, M28W800B
Table 14. CFI Query System Interface Information
Offset 1Bh Data 0027h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Note: This value must be 0000h if no VPP pin is present VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Note: This value must be 0000h if no VPP pin is present Typical timeout per single byte/word program (multi-byte program count = 1), 2n s (if supported; 0000h = not supported) Typical timeout for maximum-size multi-byte program or page write, 2n s (if supported; 0000h = not supported) Typical timeout per individual block erase, 2n ms (if supported; 0000h = not supported) Typical timeout for full chip erase, 2n ms (if supported; 0000h = not supported) Maximum timeout for byte/word program, 2n times typical (offset 1Fh) (0000h = not supported) Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h) (0000h = not supported) Maximum timeout per individual block erase, 2n times typical (offset 21h) (0000h = not supported) Maximum timeout for chip erase, 2n times typical (offset 22h) (0000h = not supported)
1Ch
0036h
1Dh
00B4h
1Eh
00C6h
1Fh 20h 21h 22h 23h 24h 25h 26h
0005h 0000h 000Ah 0000h 0007h 0000h 0003h 0000h
14/40
M28W800T, M28W800B
Table 15. Device Geometry Definition
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch Data 0014h 0001h 0000h 0000h 0000h 0002h Device Size = 2n in number of bytes Flash Device Interface Code description: Asynchronous x16 Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within device bit 7 to 0 = x = number of Erase Block Regions Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more contiguous Erase Blocks of the same size. For example, a 128KB device (1Mb) having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is considered to have 5 Erase Block Regions. Even though two regions both contain 16KB blocks, the fact that they are not contiguous means they are separate Erase Block Regions. 3. By definition, symmetrically block devices have only one blocking region. M28W800T 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h M28W800B 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h M28W800T 000Fh 0000h 0000h 0001h 0007h 0000h 0020h 0000h M28W800B 0007h 0000h 0020h 0000h 000Fh 0000h 0000h 0001h Erase Block Region Information bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in size. The value z = 0 is used for 128 byte block size. e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase Block Region: e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") Note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 Description
15/40
M28W800T, M28W800B
Table 16. Primary Algorithm-Specific Extended Query Table
Offset (P)h = 35h Data 0050h 0052h 0049h (P+3)h = 38h (P+4)h = 39h (P+5)h = 3Ah 0031h 0030h 0006h 0000h (P+7)h (P+8)h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm bit 0 bit 1 bit 2 bit 3 bit 4 bit 31 to 5 Chip Erase supported (1 = Erase Suspend supported (1 = Program Suspend (1 = Lock/Unlock supported (1 = Quequed Erase supported (1 = Reserved; undefined bits are `0' Yes, 0 = Yes, 0 = Yes, 0 = Yes, 0 = Yes, 0 = No) No) No) No) No) Primary Algorithm extended Query table unique ASCII string "PRI" Description
(P+9)h = 3Eh
0001h
Supported Functions after Suspend Read Array, Read Status Register and CFI Query are always supported during Erase or Program operation bit 0 bit 7 to 1 Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are `0'
(P+A)h = 3Fh (P+B)h
0000h 0000h
Block Lock Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block Lock Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0'
(P+C)h = 41h
0027h
VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV
(P+D)h = 42h
00C0h
VPP Supply Optimum Program/Erase voltage bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV
(P+E)h
0000h
Reserved
Table 17. Security Code Area
Offset 80h 81h 82h 83h 84h 85h 86h 87h Data 00XX 00XX 00XX 00XX 00XX 00XX 00XX 00XX 64 Pseudo random bit unique security number Description
16/40
M28W800T, M28W800B
Table 18A. DC Characteristics (TA = 0 to 70C or -40 to 85C)
Symbol ILI ILO ICC ICC1 ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby or Automatic Standby) Supply Current (Power Down) Test Condition 0V VIN VDD 0V VOUT VDD E = VSS, G = VIH, f = 5MHz E = VDD 0.2V, RP = VDD 0.2V RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD E = VIH, Erase suspended VPP > VDD VPP VDD RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD Program/Erase suspended -0.4 VDDQ -0.4 IOL = 100A, VDD = VDD min, VDDQ = VDDQ min IOH = -100A, VDD = VDD min, VDDQ = VDDQ min VDDQ -0.1 2.7 11.4 3.6 12.6 2.2 1.5 1.5 0.1 VDD = 2.7V to 3.6V VDDQ = 2.7V to 3.6V Min Max 1 10 20 10 10 20 20 20 20 10 200 15 5 15 20 15 20 200 0.4 A A mA A A mA mA mA mA A A A A mA mA mA mA A V V V V V V V V V Unit
ICC3
Supply Current (Program)
ICC4
Supply Current (Erase)
ICC5 IPP IPP1 IPP2
Supply Current (Program/Erase Suspend) Program Current (Read or Standby) Program Current (Read or Standby) Program Current (Power Down)
IPP3
Program Current (Program)
IPP4
Program Current (Erase)
IPP5 (1) VIL VIH VOL VOH VPP1 VPPH VLKO VLKO2 VPPLK
Program Current (Program/Erase Suspend) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Program Voltage (Program or Erase operations) Program Voltage (Program or Erase operations) VDD Supply Voltage (Program and Erase lock-out) VDDQ Supply Voltage (Program and Erase lock-out) Program Voltage lock-out
Note: 1. Current increases to I CC + ICC5 during a Read operation.
17/40
M28W800T, M28W800B
Table 18B. DC Characteristics (TA = 0 to 70C or -40 to 85C)
Symbol ILI ILO ICC ICC1 ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby or Automatic Standby) Supply Current (Power Down) Test Condition 0V VIN VDD 0V VOUT VDD E = VSS, G = VIH, f = 5MHz E = VDD 0.2V, RP = VDD 0.2V RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD E = VIH, Erase suspended VPP > VDD VPP VDD RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD Program/Erase suspended -0.2 VDDQ -0.2 IOL = 100A, VDD = VDD min, VDDQ = VDDQ min IOH = -100A, VDD = VDD min, VDDQ = VDDQ min VDDQ -0.1 2.7 11.4 3.3 12.6 2.2 1.2 1.5 0.1 VDD = 2.7V to 3.3V VDDQ = 1.65V min Min Max 1 10 20 10 10 20 20 20 20 10 200 15 5 15 20 15 20 200 0.2 A A mA A A mA mA mA mA A A A A mA mA mA mA A V V V V V V V V V Unit
ICC3
Supply Current (Program)
ICC4
Supply Current (Erase)
ICC5 IPP IPP1 IPP2
Supply Current (Program/Erase Suspend) Program Current (Read or Standby) Program Current (Read or Standby) Program Current (Power Down)
IPP3
Program Current (Program)
IPP4
Program Current (Erase)
IPP5 (1) VIL VIH VOL VOH VPP1 VPPH VLKO VLKO2 VPPLK
Program Current (Program/Erase Suspend) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Program Voltage (Program or Erase operations) Program Voltage (Program or Erase operations) VDD Supply Voltage (Program and Erase lock-out) VDDQ Supply Voltage (Program and Erase lock-out) Program Voltage lock-out
Note: 1. Current increases to I CC + ICC5 during a Read operation.
18/40
M28W800T, M28W800B
Table 19. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to VDDQ VDDQ/2
1N914
Figure 5. AC Testing Load Circuit
VDDQ/2
3.3k
Figure 4. AC Testing Input Output Waveform
DEVICE UNDER TEST CL = 50pF VDDQ/2 0V
AI00610
OUT
VDDQ
CL includes JIG capacitance
AI00609B
Table 20. Capacitance (1) (TA = 25 C, f = 1 MHz )
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
19/40
M28W800T, M28W800B
Table 21A. Read AC Characteristics (1) (TA = 0 to 70C or -40 to 85C)
M28W800 100 Symbol Alt Parameter VDD = 3V to 3.6V VDDQ = 2.7V min Min tAVAV tAVQV tPHQV tELQX (2) tELQV (3) tGLQX (2) tGLQV (3) tEHQX (2) tEHQZ (2) tGHQX (2) tGHQZ (2) tAXQX (2) tPLPH (2,4)
Note: 1. 2. 3. 4.
120 VDD = 2.7V to 3.3V VDDQ = 1.65V min Min 120 100 200 120 200 0 100 120 0 30 35 0 25 30 0 25 30 0 100 Max
Unit
Max
tRC tACC tPWH tLZ tCE tOLZ tOE tOH tHZ tOH tDF tOH tRP
Address Valid to Next Address Valid Address Valid to Output Valid Power Down High to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Transition to Output Transition RP Reset Pulse Width
100
ns ns ns ns ns ns ns ns ns ns ns ns ns
0
0
0
0
0 100
See AC Testing Measurement conditions for timing measurements. Sampled only, not 100% tested. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV . The device Reset is possible but not guaranteed if tPLPH < 100ns.
20/40
M28W800T, M28W800B
Table 21B. Read AC Characteristics (1) (TA = 0 to 70C or -40 to 85C)
M28W800 150 Symbol Alt Parameter VDD = 2.7V to 3.3V VDDQ = 1.65V min Min tAVAV tAVQV tPHQV tELQX (2) tELQV (3) tGLQX (2) tGLQV (3) tEHQX (2) tEHQZ (2) tGHQX (2) tGHQZ (2) tAXQX (2) tPLPH (2,4)
Note: 1. 2. 3. 4.
Unit
Max ns 150 200 ns ns ns 150 ns ns 40 ns ns 35 ns ns 35 ns ns ns
tRC tACC tPWH tLZ tCE tOLZ tOE tOH tHZ tOH tDF tOH tRP
Address Valid to Next Address Valid Address Valid to Output Valid Power Down High to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Transition to Output Transition RP Reset Pulse Width
150
0
0
0
0
0 100
See AC Testing Measurement conditions for timing measurements. Sampled only, not 100% tested. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV . The device Reset is possible but not guaranteed if tPLPH < 100ns.
21/40
22/40
tAVAV VALID tAVQV tAXQX tELQV tELQX tEHQX tEHQZ tGLQV tGLQX VALID tPHQV tGHQX tGHQZ ADDRESS VALID AND CHIP ENABLE OUTPUTS ENABLED DATA VALID STANDBY
AI02610
M28W800T, M28W800B
Figure 6. Read AC Waveforms
A0-A18
E
G
DQ0-DQ15
RP
POWER-UP AND STANDBY
Note: Write Enable (W) = High.
M28W800T, M28W800B
Table 22A. Write AC Characteristics, Write Enable Controlled (1) (TA = 0 to 70C or -40 to 85C)
M28W800 100 Symbol Alt Parameter VDD = 3V to 3.6V VDDQ = 2.7V min Min tAVAV tPHWL tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWH tWPHWH tVPHWH (4) tWHAX tWHQV1 (2, 3) tWHQV2 (2) tWHQV3 (2) tQVVPL (4) tPLPH (4,5) tPLRH (4,6)
Note: 1. 2. 3. 4. 5. 6.
120 VDD = 2.7V to 3.3V VDDQ = 1.65V min Min 120 120 0 70 70 0 0 30 70 70 200 0 10 4 5 4 5 0 100 22 22 Max ns ns ns ns ns ns ns ns ns ns ns ns s sec sec ns ns s Unit
Max
tWC tPS tCS tWP tDS tDH tCH tWPH tAS
Write Cycle Time Power Down High to Write Enable Low Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Data Valid to Write Enable High Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable High Write Protect High to Write Enable High
100 100 0 70 70 0 0 30 70 70 200 0 10
tVPS tAH
VPP High to Write Enable High Write Enable High to Address Transition Write Enable High to Output Valid Write Enable High to Output Valid (Parameter Block Erase) Write Enable High to Output Valid (Main Block Erase) Output Valid to VPP not VDD nor VPPH
0 100
tRP
RP Reset Pulse Width RP Low to Program/Erase Abort
See AC Testing Measurement conditions for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. For Program or Erase of the Lockable Blocks WP must be at VIH. Sampled only, not 100% tested. The device Reset is possible but not guaranteed if tPLPH < 100ns. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase m
23/40
M28W800T, M28W800B
Table 22B. Write AC Characteristics, Write Enable Controlled (1) (TA = 0 to 70C or -40 to 85C)
M28W800 150 Symbol Alt Parameter VDD = 2.7V to 3.3V VDDQ = 1.65V min Min tAVAV tPHWL tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWH tWPHWH tVPHWH (4) tWHAX tWHQV1 (2, 3) tWHQV2 (2) tWHQV3 (2) tQVVPL (4) tPLPH (4,5) tPLRH (4,6)
Note: 1. 2. 3. 4. 5. 6.
Unit
Max ns ns ns ns ns ns ns ns ns ns ns ns s 4 5 sec sec ns ns 22 s
tWC tPS tCS tWP tDS tDH tCH tWPH tAS
Write Cycle Time Power Down High to Write Enable Low Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Data Valid to Write Enable High Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable High Write Protect High to Write Enable High
150 150 0 100 100 0 0 50 100 100 200 0 10
tVPS tAH
VPP High to Write Enable High Write Enable High to Address Transition Write Enable High to Output Valid Write Enable High to Output Valid (Parameter Block Erase) Write Enable High to Output Valid (Main Block Erase) Output Valid to VPP not VDD nor VPPH
0 100
tRP
RP Reset Pulse Width RP Low to Program/Erase Abort
See AC Testing Measurement conditions for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. For Program or Erase of the Lockable Blocks WP must be at VIH. Sampled only, not 100% tested. The device Reset is possible but not guaranteed if tPLPH < 100ns. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode.
24/40
PROGRAM OR ERASE tAVAV VALID tAVWH tWHAX
A0-A18
E tWHEH
tELWL
G tWHWL
W tWLWH tWHQV1,2,3 tWHDX COMMAND CMD or DATA STATUS REGISTER
Figure 7. Write AC Waveforms, W Controlled
tDVWH
DQ0-DQ15
tPHWL
RP
tWPHWH
WP
tVPHWH
tQVVPL
VPP
POWER-UP AND SET-UP COMMAND
CONFIRM COMMAND OR DATA INPUT
STATUS REGISTER READ
M28W800T, M28W800B
Note: Command Input and Status Register Read Output is on DQO-DQ7 only.
AI02611
25/40
M28W800T, M28W800B
Table 23A. Write AC Characteristics, Chip Enable Controlled (1) (TA = 0 to 70C or -40 to 85C)
M28W800 100 Symbol Alt Parameter VDD = 3V to 3.6V VDDQ = 2.7V min Min tAVAV tPHEL tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEH tWPHEH tVPHEH (4) tEHAX tEHQV1 (2, 3) tEHQV2 (2) tEHQV3 (2) tQVVPL (4) tPLPH (4,5) tPLRH (4,6)
Note: 1. 2. 3. 4. 5. 6.
120 VDD = 2.7V to 3.3V VDDQ = 1.65V min Min 120 120 0 70 70 0 10 30 70 70 200 0 10 4 5 4 5 0 100 22 22 Max ns ns ns ns ns ns ns ns ns ns ns ns s sec sec ns ns s Unit
Max
tWC tPS tCS tCP tDS tDH tWH tCPH tAS
Write Cycle Time Power Down High to Chip Enable Low Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Data Valid to Chip Enable High Chip Enable High to Data Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable High Write Protect High to Chip Enable High
100 100 0 70 70 0 0 30 70 70 200 0 10
tVPS tAH
VPP High to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Output Valid Chip Enable High to Output Valid (Parameter Block Erase) Chip Enable High to Output Valid (Main Block Erase) Output Valid to VPP not VDD nor VPPH
0 100
tRP
RP Reset Pulse Width RP Low to Program/Erase Abort
See AC Testing Measurement conditions for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. For Program or Erase of the Lockable Blocks WP must be at VIH. Sampled only, not 100% tested. The device Reset is possible but not guaranteed if tPLPH < 100ns. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode.
26/40
M28W800T, M28W800B
Table 23B. Write AC Characteristics, Chip Enable Controlled (1) (TA = 0 to 70C or -40 to 85C)
M28W800 150 Symbol Alt Parameter VDD = 2.7V to 3.3V VDDQ = 1.65V min Min tAVAV tPHEL tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEH tWPHEH tVPHEH (4) tEHAX tEHQV1
(2, 3)
Unit
Max ns ns ns ns ns ns ns ns ns ns ns ns s 4 5 sec sec ns ns 22 s
tWC tPS tCS tCP tDS tDH tWH tCPH tAS
Write Cycle Time Power Down High to Chip Enable Low Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Data Valid to Chip Enable High Chip Enable High to Data Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable High Write Protect High to Chip Enable High
150 150 0 100 100 0 0 50 100 100 200 0 10
tVPS tAH
VPP High to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Output Valid Chip Enable High to Output Valid (Parameter Block Erase) Chip Enable High to Output Valid (Main Block Erase) Output Valid to VPP not VDD nor VPPH
tEHQV3 (2) tEHQV4
(2)
tQVVPL (4) tPLPH
(4,5)
0 100
tRP
RP Reset Pulse Width RP Low to ProgramErase Abort
tPLRH (4,6)
Note: 1. 2. 3. 4. 5. 6.
See AC Testing Measurement conditions for timing measurements. Time is measured to Status Register Read giving bit b7 = '1'. .For Program or Erase of the Lockable Blocks WP must be at VIH. Sampled only, not 100% tested. The device Reset is possible but not guaranteed if tPLPH < 100ns. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode.
27/40
28/40
PROGRAM OR ERASE tAVAV VALID tAVEH tEHAX tEHWH tEHEL tELEH tEHQV1,2,3 tEHDX COMMAND CMD or DATA STATUS REGISTER tWPHEH tVPHEH tQVVPL CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ
AI02612
A0-A18
M28W800T, M28W800B
W
tWLEL
G
Figure 8. Write AC Waveforms, E Controlled
E
tDVEH
DQ0-DQ15
tPHEL
RP
WP
VPP
POWER-UP AND SET-UP COMMAND
M28W800T, M28W800B
Figure 9. Reset/Power Down AC Waveform
Reset during Read Mode tPLPH RP tPHQV
Reset during Program with tPLPH tPLRH Abort Complete tPLRH tPLPH RP
tPHWL tPHEL
Reset during Program/Erase with tPLPH > tPLRH Abort Power Complete Down tPLRH tPLPH RP
AI00624
tPHWL tPHEL
29/40
M28W800T, M28W800B
Figure 10. Program Flowchart and Pseudo Code
Start
Write 40h Command
Write Address & Data
PG instruction: - write 40h command - write Address & Data (memory enters read status state after the PG instruction)
Read Status Register
do: - read status register (E or G must be toggled) NO
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
while b7 = 1
NO
VPP Invalid Error (1, 2)
If b3 = 1, VPP invalid error: - error handler
NO
Program Error (1, 2)
If b4 = 1, Program error: - error handler
NO
Program to Protected Block Error
If b1 = 1, Program to Protected Block Error: - error handler
AI00611B
Note: 1. Status check of b1 (Protected Block), b3 (V PP Invalid) and b4 (Program Error) can be made after each word programming or after a sequence. 2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
30/40
M28W800T, M28W800B
Figure 11. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h Command
Write 70h Command
PES instruction: - write B0h command (memory enters read register state after the PES instruction) do: - read status register (E or G must be toggled)
Read Status Register
b7 = 1 YES b4 = 1 YES Write FFh Command
NO
while b7 = 1
NO
Program Complete
If b4 = 0, Program completed (at this point the memory will accept only the RD or PER instruction)
RD instruction: - write FFh command - one or more data reads from another block
Read data from another block
Write D0h Command
Write FFh Command
Program Continues
Read Data
PER instruction: - write D0h command to resume erasure - if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued).
AI00612
31/40
M28W800T, M28W800B
Figure 12. Erase Flowchart and Pseudo Code
Start
Write 20h Command
Write Block Address & D0h Command
EE instruction: - write 20h command - write Block Address (A12-A17) & command D0h (memory enters read status state after the EE instruction)
Read Status Register
NO Suspend
YES
do: - read status register (E or G must be toggled) if EE instruction given execute suspend erase loop while b7 = 1
b7 = 1
NO
Suspend Loop
YES b3 = 0 YES b4, b5 = 0 YES b5 = 0 YES b1 = 0 YES End
AI00613B
NO
VPP Invalid Error (1)
If b3 = 1, VPP invalid error: - error handler
NO
Command Sequence Error
If b4, b5 = 1, Command Sequence error: - error handler
NO
Erase Error (1)
If b5 = 1, Erase error: - error handler
NO
Erase to Protected Block Error
If b1 = 1, Erase to Protected Block Error: - error handler
Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
32/40
M28W800T, M28W800B
Figure 13. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h Command
Write 70h Command
PES instruction: - write B0h command (memory enters read register state after the PES instruction) do: - read status register (E or G must be toggled)
Read Status Register
b7 = 1 YES b6 = 1 YES Write FFh Command
NO
while b7 = 1
NO
Erase Complete
If b6 = 0, Erase completed (at this point the memory wich accept only the RD or PER instruction)
RD instruction: - write FFh command - one o more data reads from another block PG instruction: - write 40h command - write Address & Data
Read data from another block or Program
Write D0h Command
Write FFh Command
Program Continues
Read Data
PER instruction: - write D0h command to resume erasure - if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued).
AI00615
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M28W800T, M28W800B
Figure 14A. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR COMMAND WRITE (1)
90h YES READ SIGNATURE
NO
98h YES CFI QUERY
NO
70h YES READ STATUS
NO
50h YES CLEAR STATUS
NO
READ ARRAY
40h or 10h YES PROGRAM SET-UP
NO
20h YES
NO
READ STATUS
C ERASE SET-UP FFh YES D0h YES NO NO
B
A
ERASE COMMAND ERROR
AI00616
Note: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or if VDD falls below VLKO, the Command Interface defaults to Read Array mode. 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
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M28W800T, M28W800B
Figure 14B. Command Interface and Prgogram Erase Controller Flowchart (b)
B A
ERASE
(READ STATUS)
YES
READY (2) NO NO
B0h YES
READ STATUS ERASE SUSPEND
YES
READY (2) NO
ERASE NO SUSPENDED
READ STATUS
YES READ STATUS YES
70h NO
READ SIGNATURE
YES
90h NO
CFI QUERY
YES
98h NO
PROGRAM SET-UP c READ ARRAY
AI00617
YES
40h or 10h NO
NO
D0h
YES
READ STATUS
(ERASE RESUME)
Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
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M28W800T, M28W800B
Figure 14C. Command Interface and Program Erase Controller Flowchart (c)
B
C
PROGRAM
(READ STATUS)
YES
READY (2) NO NO
B0h YES
READ STATUS PROGRAM SUSPEND
YES
READY (2) NO
NO
PROGRAM SUSPENDED YES
READ STATUS
READ STATUS
YES
70h NO
READ SIGNATURE
YES
90h NO
CFI QUERY
YES
98h NO
READ ARRAY
AI00618
NO
D0h
YES
READ STATUS
(PROGRAM RESUME)
Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
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M28W800T, M28W800B
Table 24. Ordering Information Scheme
Example: Device Type M28 Operating Voltage W = VDD = 2.7V to 3.6V; VDDQ = 1.65V or 2.7V Device Function 800 = 8 Mbit (512Kb x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 100 = 100 ns 120 = 120 ns 150 = 150 ns Package N = TSOP48: 12 x 20 mm GB = BGA48: 0.75 mm pitch Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option T = Tape & Reel Packing M28W800T 100 N 6 T
Devices are shipped from the factory with the memory content erased (to FFFFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M28W800T, M28W800B
Table 25. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data
mm Symb Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 11.90 - 0.50 0 48 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 12.10 - 0.70 5 0.020 0.002 0.037 0.007 0.004 0.780 0.720 0.469 - 0.020 0 48 0.004 Typ Min Max 0.047 0.006 0.041 0.011 0.008 0.795 0.728 0.476 - 0.028 5 inches
Figure 15. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Drawing is not to scale.
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M28W800T, M28W800B
Table 26. BGA48 - 8 x 6 balls, 0.75 mm pitch, Package Mechanical Data
mm Symb Typ A A1 A2 b ddd D D1 e E E1 SD SE 0.735 0.250 0.485 0.350 - 6.620 3.750 0.750 6.800 5.250 0.375 0.375 Min 0.635 0.200 0.435 0.300 - 6.520 - - 6.700 - - - Max 0.835 0.300 0.535 0.400 0.080 6.720 - - 6.900 - - - Typ 0.029 0.010 0.019 0.014 - 0.261 0.148 0.030 0.267 0.207 0.015 0.015 Min 0.025 0.008 0.017 0.012 - 0.257 - - 0.264 - - - Max 0.033 0.012 0.021 0.016 0.008 0.265 - - 0.272 - - - inches
Figure 16. BGA48 - 8 x 6 balls, 0.75 mm pitch, Package Outline
E E1 SE BALL "A1"
D D1
SD e ddd
e
b
A A1
A2
BGA-G04
Drawing is not to scale. 39/40
M28W800T, M28W800B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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